Since Moore�s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate\nFETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to\ntackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable\ncontinued transistor scaling. In this paper, we review research on FinFETs from the bottom most device level to the topmost\narchitecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logiclevel\nand architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for\ncharacterizing FinFET devices, circuits, and architectures.
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